1. Field
The present invention relates to methods for integrating polymeric interlayer dielectric in integrated circuits.
2. Discussion of Related Art
Integrated circuits are made by forming on a substrate, such as a silicon wafer, layers of conductive material that are separated by layers of a dielectric material. These layers of dielectric material are often referred to as interlayer dielectric (ILD). Vias may be etched in the dielectric layers, then filled with a conducting material to electrically connect the separated conductive layers.
Commonly used dielectric materials include silicon dioxide (SiO2) and fluorinated glass. Although a thermally stable and mechanically strong, silicon dioxide has a relatively high dielectric constant. Demand for faster devices has resulted in smaller design rules and interconnects are becoming the limiting factor for device speed due to interconnect resistivity and delay performance. As well known, power dissipation due to resistance-capacitance (RC) becomes significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same level. Smaller line dimensions, due to stringent design rules and interconnects, increase the resistivity of the metal lines and the narrow interlines spacing increases the capacitance (C) between the lines. The speed of the device will increase as dimensions of ultra large-scale integration devices scale to smaller feature sizes ( less than 0.25 xcexcm) and larger die dimensions. But, the interconnect RC time delay of the metal interconnect will increasingly limit the performance of high speed logic chips.
Consequently, as currently practiced in the art, certain materials including various polymers that have a relatively low dielectric constant are used as dielectric materials in place of other convention high dielectric constant material such as silicon dioxide. When such materials are used in place of those with a higher dielectric constant, power dissipation due to resistance-capacitance (RC) delay may be reduced, which can enable a higher speed device.